Modern integrated circuits have become very complex due to continuous Complementary Metal Oxide Semiconductor (CMOS) scaling that has made possible integration of billions of transistors into a single multi-layer chip. Scaling to the physical device limitations and mask imprecision may have created non-determinism in the chip's characteristics, such as signal propagation delay or timing. In this environment, traditional timing characterization models and/or test methods may have limited effectiveness.
Gate-level, timing measurement and characterization may be important in many designs, run time management, and testing tasks. Manufacturing variability and operational and environmental conditions in post-silicon integrated Circuits (IC) may render timing characteristics of gate-level devices such as logic gates, transmission gates, switches, and so forth, unpredictable and/or unknown. Furthermore, with miniaturization of devices beyond 65 nm (nano-meter), the impact of intra-die variation and the spatial correlations have become more prominent. Several key areas may have been impacted. For example, the number of critical paths may be increasing with variation, rendering the traditional test methodologies based on a few critical paths inexpressive.
In statistical static timing analysis (SSTA), instead of the single valued delays utilized in traditional timing characterization models, the delay probability distributions and their correlations may be used. SSTA produces pre-silicon (i.e., pre-manufacturing) models and analysis. Recently proposed methods for IC timing measurement include post-silicon timing analysis of the ICs that integrates the SSTA models with data collected from a few on-chip test points (e.g., via ring oscillators), to estimate the chip-specific distribution of the delays. However, like other traditional timing characterization methods, the technique may be limited by the large size of modern integrated circuits, as well as MV, and operational and environmental conditions.